The present invention relates to a switching system, or more in particular to an ATM (Asynchronous Transfer Mode) switching system used with the speech path equipment of a wide-bandwidth ISDN exchange and, especially, an ATM switching system suitable for accommodating a plurality of types of input-output links having different transmission rates.
A "TDM Switching System" proposed by JP-A-59-135994 is known, for example, as an ATM switching system applied to the wide-bandwidth ISDN exchange.
This switching system comprises a multiplexer for multiplexing a fixed-length packet (hereinafter referred to as "the cell") inputted from each input line, a buffer memory for inputting a multiplexed cell, a demultiplexer for periodically separating the cells outputted from the buffer memory among output lines, and a buffer memory control circuit for controlling the buffer memory for each output line. The buffer memory control circuit, which includes FIFO (First In First Out) memories corresponding to the output lines, inputs a write address for the buffer memory into a FIFO memory corresponding to the cell output destination judged from the header information of a cell when the cell is written into the buffer memory. Also, the cell output from the buffer memory corresponding to each output line is produced at predetermined time intervals so that a read address is outputted to the buffer memory from the FIFO memory corresponding to each output line in timing with the cell output.
According to the above-mentioned prior art, the reading of a cell from the buffer memory is controlled to a predetermined timing for each output line. When an attempt is made to accommodate a plurality of types of output links (output lines) different in transmission rate in a switching system having the above-mentioned configuration, therefore, the problem is posed of a very complicated hardware configuration of the buffer memory control circuit.
A packet switching system capable of accommodating a plurality of types of input/output links having different transmission rates is proposed in JP-A63-64439, for example, as a system for controlling the write and read operations of a packet with a buffer memory using a control memory.
In the above-mentioned packet switching system, a plurality of input and output ports of a switch unit are matched one to one with input and output lines respectively, and packets are inputted and outputted to these input/output ports at a rate equal to the data transmission rate of the input/output lines connected thereto.
In order to realize this switching operation, according to the prior art, the number of an input line providing an objective of the packet write process or an output line providing an objective of the packet read process within a predetermined regular time interval and the R/W designated data are stored in the control memory according to the processing sequence in such a manner as to generate the R/W process at a frequency corresponding to the data transmission rate of each line. The contents (the line numbers and the R/W designated data) of the control memory are sequentially read with the counter output value as an address and packets are written into or read from the buffer memory for the input/output lines designated by the line number thus read out.
More specifically, the switching system described above is such that the buffer memory access is sequentially controlled in such a manner that packets are processed at the switching unit input port (or switch unit output port) connected to a high-speed input line (or output line) at a higher frequency than at the switch unit input port (or switch unit output port) connected to a low-speed input line (or output line).